Allied Telesis Patch 89262-08 Bedienungsanleitung PDF herunterladen (Seite 13)

Patch 89262-09 For AT-8900 Series Switches 13

Patch 89262-09 for Software Release 2.6.2

C613-10402-00 REV I

2.) A port was being returned to the default VLAN when deleted from one

nested VLAN even if it was still a member of another nested VLAN.

3.) A port associated with a protocol or subnet rule was not being returned

to the default VLAN when deleted from a nested VLAN.

These issues have all been resolved.

The receipt of two IP packets whose destination IP addresses were subnet

addresses caused the switch to reboot. This issue has been resolved.

Wrong bits were being set in the ASIC rule table for classifiers that matched

on IPX source socket. As the result, the classifiers would match on incorrect

values of IPX source socket. This issue has been resolved.

Some MIB values for the AT-QOS MIB, have been changed so that the

output of the switch is now compatible with the latest version of the MIB.

After the disable switch learn command had been executed successfully,

automatic MAC learning was still operating. This issue has been resolved.

If the command enable switch accelerator function=icmpredirect had been

executed, there was no resulting entry in a script subsequently created by

the create config or show config dynamic commands. This issue has been

resolved.

If two protocol VLAN association rules were added to two different

VLANs, the second protocol association rule would not work. This issue has

been resolved.

When PIM or DVMRP was enabled, if IP multicast packets were received on

the non-RPF (Reverse-Path-Forwarding) interface, i.e. the wrong ingress

interface, the CPU could become highly utilised, and the packets were not

correctly Layer 2 switched. This issue has been resolved.

Adding, or deleting, port=42 to, or from, a VLAN could cause the entire

Layer 2 Multicast Table to be cleared. This would subsequently cause high

CPU utilisation under heavy multicast traffic. This issue has been resolved.

If VRRP had been enabled on the switch, then the routing of any packets

that entered the switch via a an interface on which VRRP was operating

would be performed in software, rather than using the L3 switching process

in the ASIC. This issue has been resolved.

PCR: 40549 Module: SWI Level: 2

PCR: 40550 Module: SWMX Level: 2

PCR: 40554 Module: QoS Level: 2

PCR: 40561 Module: SWMX Level: 2

PCR: 40562 Module: SWNP Level: 2

PCR: 40565 Module: SWMX Level: 2

PCR: 40571 Module: SWMX Level: 2

PCR: 40574 Module: SWMX Level: 2

PCR: 40586 Module: SWMX Level: 2

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